WikiChip Fuse covers semiconductor and CPU architecture news, including process nodes, x86 cores, and interconnects.
HN commenters cite it for IEDM reports on SRAM scaling, TSMC process details, and CPU microarchitecture and IBM z14 coverage.
Up until now Foveros has only allowed chips to be fully stacked on top of each other. With Foveros Direct, supposely coming in Meteor Lake[1], stacked chips might also having connections from elsewhere (via the base/substrate/interposer/eimb). Previously stacked chips had to have their connectivity & power mediated through another chip, but now stacked chips are supposedly going to be able to have some of their own connectivity as well. This should enable much more interesting stacks.
Intel's process technology might have struggled for a while, but Intel has been developing absolutely top notch ways to combine chips together.
It's less a story about multi-chip, but Intel's really been figuring out how to mix and match in other ways too: the E-cores they ship everywhere are finally an Atom good enough for everyone & that do great. I feel like they've had a lot of really good projects.
Not sure how important this is, but it'll be interesting to see if they can make MCM & this all work for really low power. Intel Galileo showed huge promise as a smart device/application-processor chip, many years back. Lakefield (much bigger, more recent, mobile class) had a lot of promise as an ultraportable chip, but wasn't noticeably enough lower power at it's slower speed, but was so promising & so so small footprint (still better than a Snapdragon!). It's hard to picture the chiplet world being good for edge, good for low power: it feels more like a bigger play. But with all the mix &…
FWIW, the active channel volume is much more than a dozen atoms in a modern FinFET process.
For a ~5nm process, there might be only a few dozen atoms across the width of the fin, but the other dimensions are much larger, for a total of probably somewhere around hundreds of thousands of atoms per channel.
see e.g. https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells-2nd-gen-7nm-and-the-snapdragon-855-dtco/ and other wikichip articles for some dimension info.
but regardless, modern semiconductor manufacturing processes are incredible. the much-too-brief summary is that they shine very precise patterns of light on the silicon using very high frequency light to activate photoresist, and then etching away the silicon that isn't protected by the photoresist. this doesn't actually produce features as small as the fins, so there are a lot of tricky techniques, like doing this patterning + etching once, then growing a layer of some other material on top, then etching again to leave only the very narrow sidewalls that grew around the original feature, then etching again using the sidewalls as the pattern.
https://en.wikipedia.org/wiki/Spacer_patterning
it really is amazing - reliably writing tiny structures on stones with light.
Only an Apple engineer could answer this fully but here are some of my ideas as to why this hasn't been done yet:
-They still support playback on devices with no TEE. Kinda defeats the point of implementing it until this is the case.
- They are wary of moving more functionality into their TEE as it increases the attack surface.
- If the platform is already "attested" and locked down as it is the case today, moving the playback to the TEE provides only a little bit of extra security.
- They are banking on the ARM Realm Management Extension[0] coming to their chips. This would be more of a "catch all" solution to fuck over the owners of their machines in new and exciting ways.
[0]: https://fuse.wikichip.org/news/5699/arm-introduces-its-confidential-compute-architecture/
We discussed a different project from the same source a little over a month ago[1].
Yes, they are making transistors out of plastic[2]. ”We coat everything on that, then peel it off and reuse the glass a carriers which means we can use silicon equipment.”
That they manage to get this to work at all is amazing. I view this as a technology demonstrator more than anything else. It looks like there's a pent up demand for low end processing that this might fill.
Still no comment about this from Sam Zeloof[3] 8)
[1] - https://fuse.wikichip.org/news/6648/reincarnating-the-6502-using-flexible-tft-tech-for-iot/
[2] - https://www.eenewseurope.com/en/first-300mm-fab-for-the-uk/
[3] - https://twitter.com/szeloof
> One thing that Intel and AMD do better than any other player in the industry is branch prediction. An absolutely stupifying amount of die area is dedicated to it on x86.
Zen in particular combines an L1 perceptron and L2 TAGE[0] predictor[1]. TAGE in particular requires an immense amount of silicon, but it has something like 99.7% prediction accuracy, which is... crazy. The perceptron predictor is almost as good: 99.5%.
I wrote a software TAGE predictor, but too bad it didn't perform as well as predicted (heh) by the authors of the paper.
[0]: https://doi.org/10.1145/2155620.2155635
[1]: https://fuse.wikichip.org/news/2458/a-look-at-the-amd-zen-2-core/
AMD Zen 2 CPU and IBM z15 mainframe claims to be using TAGE branch predictor -- but this doesn't say much. The basic TAGE is quite simple (see [1]), but actual implementation likely includes loop predictor, statistical corrector predictor, perceptron hashing functions, etc.
To learn more about state of start BP look for Andre Seznec (INRIA/IRISA) and Daniel Jimenez (Texas A&M University) work. They are usually the winners of Championship Branch Prediction [2,3].
[1] https://fuse.wikichip.org/news/2458/a-look-at-the-amd-zen-2-core/
[2] https://www.jilp.org/cbp2014/program.html
[3] https://www.jilp.org/cbp2016/program.html