The CHERIoT project blog covers CHERI hardware memory-safety capabilities for embedded devices, including its RTOS, silicon, and security design.
Commenters link it to explain what CHERI is and to answer whether safe languages make it unnecessary, using its "CHERI Myths" post.
The CHERI ISA does not provide temporal safety features but it allows building temporal safety mechanisms in software. CheriBSD 23.11 includes user-space heap temporal memory safety that is enabled by default [0]. The paper "Cornucopia Reloaded: Load Barriers for CHERI Heap Temporal Safety" at ASPLOS 2024 will describe the current implementation [1].
For embedded systems, the CHERIoT [2] platform implements hardware-assisted temporal memory safety without MMU.
[0] https://ctsrd-cheri.github.io/cheribsd-getting-started/features/temporal.html
[1] https://www.asplos-conference.org/asplos2024/main-program/abstracts/#5C
[2] https://cheriot.org/papers/2023-micro-cheriot-uarch.pdf
I wonder why emulators aren't interesting for a hobbyist. However, there are FPGA implementations [1], and micro-controller-type systems on FPGA available commercially [2].
[3] has a list of publications for the rigorous engineering agenda.
1. https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-risc-v.html#cores
2. https://cheriot.org/
3. https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-formal.html
> it doesn't matter too much whether the emulator is CHERI or not since Rust itself lets me express memory safety in the type system
You might be interested in a very timely blog post: https://cheriot.org/cheri/myths/2024/08/28/cheri-myths-safe-languages.html
CHERIoT somewhat anticipated this perspective.
https://cheriot.org/cheri/myths/2024/08/28/cheri-myths-safe-languages.html
For those wondering what CHERI is: https://cheriot.org/cheri/philosophy/isa/2025/11/19/cheri-or-cheriot.html