The company blog of Codasip, a RISC-V processor IP vendor, covering processor designs, CHERI security technology and ISA licensing.
HN links it as a source on commercial CHERI hardware, RISC-V cores and ISA licensing costs, in discussions comparing RISC-V with Arm.
The place you can get a real physical commercially available CHERI implementation is RISC-V:
https://codasip.com/press-release/2023/10/31/codasip-delivers-processor-security-to-actively-prevent-cyberattacks/
That's largely because if you base a product on Arm or MIPS you have the choice of getting them to actively invest in and support you, or getting sued into oblivion by them.
THAT is why RISC-V is the most friendly ISA to innovation and where most future innovation will happen. Because innovation comes not only from internally inside Intel or Arm or MIPS (who have switched to RISC-V now anyway) but from a myriad of possible sources.
Some information I found at https://codasip.com/swerv:
The SweRV Core™ EH1 is an advanced high-performance core with small footprint, suitable for embedded devices supporting data-intensive applications such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems.
SweRV Core EH1:
Architecture: 32-bit, dual superscalar, 9-stage pipeline
Performance: Up to 4.95 CoreMark/MHz (further gain possible with compiler optimizations)
Clock speed: Up to 1.8 GHz
Technology: TSMC 28nm CMOS
Bus support: AXI, AHB-lite
Programmable Interrupt Controller
RISC-V debug support
That is not true. Two days ago lowRISC announced that OpenTitan used in Google Chromebooks will include CHERI:
https://lowrisc.org/news/opentitan-earl-grey-2-to-support-cheri-and-pqc/
Last year, Google announced that their Coral NPU will include CHERI:
https://developers.googleblog.com/en/introducing-coral-npu-a-full-stack-platform-for-edge-ai/
There are more cores that companies are actively working on:
X730 from Codasip
https://codasip.com/solutions/riscv-processor-safety-security/cheri/x730-risc-v-application-processor/
ICENI from SCI Semiconductor:
https://www.scisemi.com/products/iceni-device-family/
I suspect it's due to fundamentally different ownership forces acting on the ISAs. ARM may be a good choice now, but it's recently been put into the hands of someone who has a stake in the market which buys ARM licenses (Nvidia), and became non-neutral.
ISAs change, and there was a recent article written about this particular situation too: https://codasip.com/2020/12/22/does-isa-ownership-matter-a-tale-of-three-isas/
Whatever the 1.5% ARM royalty fee is for your org: https://www.codasip.com/2017/04/11/risc-vs-impact-on-processor-ip-licensing-fees/
For someone like Western Digital, that's probably a huge deal. I don't think it saves the RPi folks much. I suspect they get a loss leader deal. The total volume can't be that high, but it's good press for Texas Instruments.
Another risc-v:
https://www.codasip.com/2018/01/10/codasip-processors-not-affected-by-meltdown-and-spectre/