RISC-V International
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23:32 · 8K views · Dec 9, 2017
David Ditzel of Esperanto Technologies presents their massively parallel, energy-efficient RISC-V processors at the 7th RISC-V Workshop in 2017. It covers the high-performance many-core design aimed at machine learning.
Cited in RISC-V and AI hardware threads as the source for Esperanto's ambitious many-core vector design.
4 comments from Hacker News
The work Esperanto is doing take the vector concept to a mind boggling extreme: this video I want to write code for their chip!
For those interested in the RISC-V and the possibility of GPU type of things. I can mention some stuff that might not be well known. RISC-V is devloping a Vector extension (V) will allow SIMD style programming with a variable vector length. See from the last workshop: Intro: [LINK] Project Update: [LINK] Initially part of the standard was also a Vector Type field for each register, and that would have allowed different types, such as Tensors, Matrix and so on. This has been removed from the initial Vector extension proposal but work on this will continue. At least one company is already actively devloping hardware for V with Tensors (see below), sadly not open-source. This Libre GPU project is going a slightly different route targeting the Simple-V, a slimmer version of the Vector extension, Simple-V. See: [LINK] Esperanto Technology is devloping a chip (and IP) that will do this, but it will be closed source (as far as we know). See this talk by David Ditzel: this video
I'm not sure about REX, but Esperanto is pretty far away from greenarrays. From what I got out of their talk at the latest Risc-V workshop[3] (video[1], slides[2]), they're going for the big high-performance end of the spectrum. The chip they were talking about is supposed to have 16 64-bit OoO Risc-V cores and 4096 RV64GC cores with vector units connected by some sort of network on chip. [1] this video [2] [LINK] [3] [LINK]
On this talk : - this video - this video => yes and no The industry lack's of wide profiles (hardware engineer with good software understanding) is really hurting any new innovative HDL