SiFive
3 HN recommenders · recommended in 3 months, 2021
52:21 · 52K views · Apr 21, 2021
Chris Lattner's ASPLOS 2021 keynote on the golden age of compiler design in an era of hardware and software co-design, covering compiler infrastructure for accelerators and unifying hardware IRs.
Recommended for explaining where the compiler ecosystem lacks standardization for accelerators and why efforts like MLIR and CIRCT matter.
3 comments from Hacker News
I contribute to CIRCT, so I feel like I should chime in here. I personally hope that it can provide exactly the kind of unifying IRs we are all hoping for in the open-source community. The fact that the tools are implemented in C++ may be a win for some, but I think the CIRCT project is compelling for much deeper reasons. The README states the ambition clearly: > By working together, we hope that we can build a new center of gravity to draw contributions from the small (but enthusiastic!) community of people who work on open hardware tooling. There are weekly community meetings that are open to the public, and we have guest speakers from all sorts of interesting projects in the open-source community. Many of those are leading to collaborations and contributions to CIRCT. There hasn't been much (any?) discussion of CIRCT on HN, but rather than present the reasons I think it's so great here, I'll point to a talk[1] I gave earlier this year and a much better talk[2] Chris Lattner gave shortly thereafter, both of which lead up to the "Why CIRCT?" question in the second half. Looking back at that SymbiFlow thread, I see familiar faces that are now actively contributing to CIRCT. There are mentions of many different hardware IRs in some of the posts, but at least three have first-class support in CIRCT today: FIRRTL[3], LLHD[4], and Calyx[5]. This is all very recent and experimental, but I would say the results are already promising. [1] [LINK] [2] this video [3] [LINK] [4] [LINK] [5]
They've tried variations of this. It takes instruction bits to describe these registers: 32 regs is 5 bits, target + src1 + src2 is 15 bits already. They've tried scratch pads. The Mill CPU's Belt is yet another approach. [LINK] [LINK] How to Use 1000 Registers [LINK] 1000 registers would be 10 bits. So they tried register windows. These are all good ideas but they get to compete. So far, I'm a huge AArch64 fan but I now see the purpose of RISC-V. I watched Chris Lattner's ASPLOS talk and it finally clicked. this video
You might like this talk that describes parts of the compiler ecosystem that are lacking standardization for accelerators this video