Jan Gray's site on FPGA computing, covering the GRVI Phalanx RISC-V many-core design, FPGA tooling, and chip process news.
Commenters credit Jan Gray as a pioneer of soft-core FPGA design and link his papers on GRVI Phalanx cluster applications and the xr16.
Author: Thanks for taking the time to reply.
I read the write-up with a LOT of interest, this is really amazing work, there's not a lot of good options for auto-routing with open-source PCB tools (i.e. KiCad). I have also used the other autorouter you mentioned for "low-complexity" boards in KiCad and it helped do the job but was painful.
In my career I've also used the autorouter built into the "high-end" PCB tools and they could handle the complexity of boards you outlined WITHOUT needing a massive GPU, but they also paid people to improve this stuff over 15-to-20-years and development happened when single-core computers with limited RAM were the norm.
On the technical side, somewhat more recent FPGA 'placement' algorithms used a simulated annealing algorithm, while what you didn't isn't about placement, that approach could posisbly help with 'net cross-over reduction' type of passes, and maybe help with designs where you can do port swap / pin swap.
I'm amused you made a RISC-V array with discrete parts -- I'm sure you considered using an FPGA? Jan Gray has done > 1000+ RISC-V cores (https://fpga.org/grvi-phalanx/) in "older" Xilinx FPGAs.
If you're trying to emulate Thinking Machines / CM-x or anything else, frankly I think a "mondo" FPGA is still the way to go.
Job-wise: A suggestion might be to reach out to the guys at AllSpice ( allspice.io ) who make revision control software for Altium and possibly KiCad. The work you did to enable IPC, etc seems like…
Jan Gray is, I think, more-or-less the Godfather of this approach. I especially enjoyed his Circuit Cellar 3-part series where he describes and builds the xr16 -- a 16-bit machine whose instruction set is designed to well-match the LUT capabilities of an FPGA. I implemented it, and with the LCC C compiler, I was able to run plenty of code. Start here: https://github.com/BigEd/XSOC-xr16/blob/master/doc/xsoc-talk.pdf which is the presentation; then check out the rest of the repo doc: https://github.com/BigEd/XSOC-xr16/tree/master/doc and although it's not maintained these days, his old site is also useful: http://www.fpgacpu.org/xsoc/xr16.html for more modern stuff, see http://fpga.org/
SLM was at version 1.5 by 1988 and looking at chapter 5 suggests it had strong version number and external release management [1]
[1]: https://fpga.org/wp-content/uploads/2023/09/SLM-1.5-Guides.pdf
>What does one do with such a cluster?
They presented a short paper at FCCM '16: http://fpga.org/wp-content/uploads/2016/05/grvi_phalanx_fccm2016.pdf
Section VI lists possible applications.
Jan Gray stuffed 400 RISC-V cores into a Xilinx Kintex UltraScale KU040 FPGA (and the KU115 is three times larger, not to mention the Virtex UltraScale range).
http://fpga.org/grvi-phalanx/
More details here:
https://fpga.org/grvi-phalanx/
Do note that these are simple cores intended to compete with GPGPU use.