There were no LOAD or STORE instructions. Instead there were "address" registers (18 bits wide), matched to each "operand" (60 bit data) register.
When you updated an address register, that memory address was automatically read into the correspond operand register. Except for the last couple address registers - updating them performed a write from the corresponding operand into memory.
By our current way of thinking, it seems arse about. But it worked well when you understood it, and apparently improved concurrency. Loads and stores became sort-of transparent. (Remembering that memory was as fast, sometimes faster than the CPU, so a few instructions saved was worth the occasional unnecessary load.)
See "Design of a Computer, The Control Data 6600" by J E Thornton.
I love this book. The CDC6600 was the first architecture to implement many of paradigms that were later assigned to the RISC architecture. And Cray did it 15 years earler.
This book aims to change that in an simplified environment. I don't fault it for skipping over Karnaugh maps just like I don't fault it for skipping the physics of cosmic background radiation, or the techniques used to compensate for failures in multi-level flash memory cells. These details are not on the most direct route from (simulated) nand gates to tetris.
From a circuit board etched by someone else and PCB components purchased online and soldered together by a hobbyist, certainly, without too much difficulty (the package used by the programmable gate array requires a bit of specialty equipment, but is within reach).
One other point about Oberon is that I _believe_ that because the design predates open-source FPGA toolchains, a closed toolchain is still required to convert the Verilog (high-level design describing the processor logic) into a netlist (FPGA configuration), and it hasn't been taped out into a chip, either. So, the book covers the design of a computer end-to-middle - that is, without covering how the block / HDL level design becomes logic gates, and without covering how said gates are then manufactured. This is probably fine - the scope has to end somewhere. The linked NAND-to-Tetris articles cover the other end - from logic gates up to typical computing constructs (adder, registers, shifters, etc.).
Thornton, James E, Design of a computer: the Control Data 6600 http://ygdes.com/CDC/DesignOfAComputer_CDC6600.pdf
Gordon Bell, Computer Engineering: A DEC View of Hardware Systems Design http://research.microsoft.com/en-us/um/people/gbell/CGB%20Fi...
Levy, Henry M., Capability-Based Computer Systems http://homes.cs.washington.edu/~levy/capabook/