The RISC-V Reader

What Hacker News says

1. snvzzApr 2023
   Refer to RISC-V Reader[0].

   0. https://www.amazon.com/RISC-V-Reader-Open-Architecture-Atlas...

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2. GeorgeTirebiterMar 2022
   It depends. For some things, yes. For others, no. This is the best book ever on Risc-V (I think): https://www.amazon.com/RISC-V-Reader-Open-Architecture-Atlas... and they directly compare arm, x86, and risc-v to each other. As you'll see, "it depends".
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3. JoachimSAug 2019
   I can recommend the book The RISC-V Reader: An Open Architecture Atlas by David Patterson and Andrew Waterman.

   http://riscvbook.com/

   https://www.amazon.com/RISC-V-Reader-Open-Architecture-Atlas...

   In the book the authors compare the expressiveness (and thus code density) of code implemented with the RISC-V ISA with instructions for x86, ARM and MIPS. They show that the RISC-V ISA is able to give ARM a good fight in terms of IPC, and that it beats MIPS. (Mainly due to the delay slots which can't be filled in many real world cases.)

   They also show why the R5 should make implementations scale better in clock speed compared to ARM. This is the kind of stuff Patterson has been doing research on the last 3-4 decades, and it is quite interesting to see how this experience has guided the design of the RISC-V ISA.

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4. guerrillaNov 2021
   From the Descrption:

   "In the 1980s, Mead and Conway democratized chip design and high-level language programming surpassed assembly language programming, which made instruction set advances viable. Innovations like Reduced Instruction Set Computers (RISC), superscalar, and speculation ushered in a Golden Age of computer architecture, when performance doubled every 18 months. The ending of Dennard Scaling and Moore’s Law crippled this path; microprocessor performance improved only 3% last year! In addition to poor performance gains, Spectre recently demonstrated timing attacks on modern microprocessors that leak information at high rates.

   The ending of Dennard scaling and Moore’s law and the deceleration of performance gains for standard microprocessors are not problems that must be solved but facts that if accepted offer breathtaking opportunities. We believe high-level, domain-specific languages and architectures, freeing architects from the chains of proprietary instruction sets, and the demand from the public for improved security will usher in a new Golden Age for computer architecture. Aided by open source ecosystems, agilely developed chips will convincingly demonstrate advances and thereby accelerate commercial adoption. The instruction set philosophy of the general-purpose processors in these chips will likely be RISC, which has stood the test of time. We envision the same rapid improvement as in the last Golden Age, but this time in cost, energy, and security as well as in performance."

   "David Patterson is a professor emeritus of Computer Science at UC Berkeley, a distinguished engineer at Google, and Vice-Chair of the Board of Directors of the RISC-V Foundation. He received his BA, MS, and PhD degrees from UCLA. His most successful research projects were likely Reduced Instruction Set Computer (RISC), Redundant Array of Inexpensive Disks (RAID), and Network of Workstation (NOW). All three projects helped lead to multibillion-dollar industries. This research led to many papers and seven books, with the best known being Computer Architecture: A Quantitative Approach co-authored by John Hennessy, now in its sixth edition. His most recent book is The RISC-V Reader: An Open Architecture Atlas , co-authored by Andrew Waterman.

   Patterson is a member of the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. His teaching was honored with the ACM Karlstrom Award and the IEEE Mulligan Medal. As a past president of ACM and a past Chair of CRA, he received Distinguished Service Awards from ACM, CRA, and SIGARCH and the Tapia Achievement Award for Scientific Scholarship, Civic Science, and Diversifying Computing."

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