VHDL for logic synthesis

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1. bmitcDec 2020
   I am currently using a Digilent Nexys A7-100T.

   https://store.digilentinc.com/nexys-a7-fpga-trainer-board-re...

   It has a USB host port for a keyboard and VGA out for the display. The jury is still out as to whether I can build the entire CPU using nand gates, including the ROM and RAM memory. Doing so will use a lot of the FPGA's resources from calculations I've seen. If that's not possible for the memory, then I plan on using the block RAM that's included on the Xilinx board, but for everything else I plan on following the book's design as close as possible. So far, I am in chapters 1-3 simply porting my solutions in the course's HDL to VHDL, which is relatively straightforward so far. I'm taking my time to make sure I'm doing things "professionally", as I'd like to learn the Xilinx toolchain in my professional work at some point. My experience with FPGAs has been implementing them with LabVIEW, which actually makes learning VHDL somewhat mechanical although a bit frustrating. (If I had an FPGA big enough that's targetable via LabVIEW, I could probably build and test the computer in a day or two aside from the VGA and keyboard.) The combinatorial gates are done now, and I've implemented a DFF and am building things from there. So now I'm learning about clocking and such with VHDL. The most troublesome part I anticipate is what to do about the ROM and RAM memory and the display and keyboard. I'd also like to update the CPU where I can interactively download new code to the CPU from a PC using the assembler and software stack I'm building, which is in F#.

   I have several books I am using as reference:

   - VHDL By Example by Blaine C. Readler (great first intro to VHDL)

   - Digital Design Using Digilent FPGA Boards: VHDL/Vivado Edition by Haskell and Hanna

   - Effective Coding with VHDL: Principles and Best Practices by Ricardo Jasinski (I'm using this to sort through the various ways to do things in VHDL and have best practices in my code.)

   - VHDL for Logic Synthesis by Andrew Rushton

   - FPGA Prototyping by VHDL Examples: Xilinx MicroBlaze MCS SoC by Pong Chu

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2. panpannaJul 2020
   Writing this with good intentions, not trying to start a fight...

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   There are some minor issues with your code that shows you are probably a verilog/SV guy and not an experienced VHDL guy.

   Please read Andrew Rushtons "VHDL for Logic Synthesis". I also recommend you read on VHDLs 9-valued logic and why it was designed this way and how it differs from verilogs Bit.

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