Travis Downs

Absolutely. It's useful in text processing, it's useful in emulation, it's useful for doing bit-math for various encodings and checksumming, etc. The newer revisions don't have any downclocking either.

https://old.reddit.com/r/emulation/comments/lzfpz5/what_are_the_implications_of_avx512_for_emulation/

https://travisdowns.github.io/blog/2020/08/19/icl-avx512-freq.html

People have made some incredibly broad assertions about the technology as a whole on the basis of a first-gen product that lingered on the market for far too long because of the 10nm woes.

People also hang on Linus's words far, far too much. He's incredibly toxic and willing to opine about stuff he's been disconnected from for 20 years. Lisa Su is putting her money where her mouth is, AMD is making a billion-dollar bet on AVX-512 at a time when Intel has actually abandoned it in the consumer market entirely. Maybe she's doing it just for the server market, but that still means she thinks server-market customers are going to see an actual benefit on normal server tasks, such that it will be worth making every single customer pay more for a larger piece of silicon.

It's not the kind of thing you do "just to win a couple HPC benchmarks". Sorry, I trust the person with the financial stake in this discussion a lot more than I trust Linus's spit-takes.

> Additionally, 512-bit wide vectors are just too big - the resulting vector units take up too much die space even on big cores, and the power consumption causes issues causing said dies to downclock.

This is no longer true, citing [0]:

> At least, it means we need to adjust our mental model of the frequency related cost of AVX-512 instructions. Rather than the prior-generation verdict of “AVX-512 generally causes significant downclocking”, on these Ice Lake and Rocket Lake client chips we can say that AVX-512 causes insignificant (usually, none at all) license-based downclocking and I expect this to be true on other ICL and RKL client chips as well.

And we still have to see AMDs implementation of AVX512 on Zen4 to know what behavior and limits it may have (if any).

[0] https://travisdowns.github.io/blog/2020/08/19/icl-avx512-freq.html

The three links in the third paragraph of the article describe the meaning of license in this context:

https://stackoverflow.com/a/56861355

https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html

https://lemire.me/blog/2018/09/07/avx-512-when-and-how-to-use-these-new-instructions/

Excerpted from the Stack Overflow answer:

There are three frequency levels, so-called licenses, from fastest to slowest: L0, L1 and L2. L0 is the "nominal" speed you'll see written on the box: when the chip says "3.5 GHz turbo", they are referring to the single-core L0 turbo. L1 is a lower speed sometimes called AVX turbo or AVX2 turbo, originally associated with AVX and AVX2 instructions. L2 is a lower speed than L1, sometimes called "AVX-512 turbo".

>Because I've actually benchmarked it: https://quick-bench.com/q/ISEetAHOohv-GaEuYR-7MajJgTc
18.5 nanoseconds fits under no reasonable definition of "crazy expensive", not when a regular increment clocks in at 5.9 nanoseconds. And there is extremely few situations where you increment a reference count more than, like, 5 times. It's just not an issue.

Congratulations. You tested a construct meant for multicore/threading
in a single threaded benchmark and then marvel at the low overhead.

Of course you will only start seeing the cost if there is actually contention to operate on the value between multiple threads running simultaniously.
See.: https://travisdowns.github.io/blog/2020/07/06/concurrency-costs.html

Yes, but I also mean that parallelism to be atomic/non-locking. afaik only Java/C# can do this on a high-level (without going back to atomic arrays in C) but I still can't explain why, the best I found so far is:

"Many lock-free structures offer atomic-free read paths, notably concurrent containers in garbage collected languages, such as ConcurrentHashMap in Java. Languages without garbage collection have fewer straightforward options, mostly because safe memory reclamation is a hard problem..." - Travis Downs https://travisdowns.github.io/blog/2020/07/06/concurrency-costs.html

But it seems there is also some benefit to have a VM in addition to a GC for this joint/atomic parallelism.

Thanks for that summary.

I'm working on a system where references can be passed around at runtime. Can references in Pony be passed around at runtime between threads.

I'm working on ideas such as:

- all threads reading or writing at the same time. This is how I think GPUs work.

- I am working how to parallelise the bank transfer problem. You have bank accounts of money and want to transfer money between them but never deduct below 0. So you need consistency on an accounts balance. I was looking at sharding the data. I want to get more than 1 million transfers a second.

This article is good.
https://travisdowns.github.io/blog/2020/07/06/concurrency-costs.html