Tom Verbeure writes about electronics hobby projects, FPGA design, RISC-V cores, test equipment teardowns, and video signal tools.
HN links it for his FPGA and electronics projects, such as the fake parallel printer capture tool, and he describes his steady blogging pace.
> unsubstantiated claims
Indeed:
> It used to be easy to have any kind of X client connect to a remote X server. Back in the early 1990s on the HP Apollo workstations in college, it was a simple matter of setting the DISPLAY environment variable, but that was before network security was a concern.
Remote controlling an HP 1670G logic analyzer with a Linux PC X server
https://tomverbeure.github.io/2023/12/26/Controlling-an-HP-1670G-with-Your-Linux-PC-X-Server.html
10 hours ago here on HN: https://news.ycombinator.com/item?id=38778807
and also:
> I recently scored a Hewlett Packard 1670A Deep Memory Logic Analyzer and I finally had a chance to fire it up. This unit dates back to 1992 and is packed with all sorts of interesting options for connecting peripherals to it. One particular feature that caught my eye was the option to connect to an X Server.
A Testament to X11 Backwards Compatibility
http://www.theresistornetwork.com/2013/12/a-testament-to-x11-backwards.html
10 years ago on HN: https://news.ycombinator.com/item?id=6850591
That's not really the full story, when this is about displays.
I currently have a display that requires Displayport 2.1 to get everything out of it, and with DSC and DP 1.4, I can get a "theoretical bitrate" that is higher than what they would normally allow. (Of course, this doesn't change what the link can do, it just allows you to do more with the same bandwidth) On thunderbolt 3 systems, the link is on HBR3, which with DSC allows 120hz, 10bit at 7680x2160. No DSC support limits the refresh to 60hz and 8bit (as then you won't have the higher rates available anyway, since DSC is mandatory with newer standards).
You can check https://tomverbeure.github.io/video_timings_calculator to see what is possible.
Alas, this is a surprisingly hard question to answer, at least for FPGA design.
Here are a few sites that helped me learn:
* https://www.fpga4fun.com
* http://fpgacpu.ca
* https://www.nandland.com/verilog/tutorials/index.html
* https://1bitsquared.com/pages/chat (Discord)
And a few interesting blogs:
* https://blackmesalabs.wordpress.com/
* https://tomverbeure.github.io
* http://labs.domipheus.com/blog/
None of the introductory FPGA books have impressed me, so I don’t have any recommendations there. Maybe some other HN readers will have some suggestions?
As in, they don't provide a user-facing way to clear the memory.
The Arbiter suffers from this: https://users.ece.cmu.edu/~dbrumley/pdf/Nighswander%20et%20al._2012_GPS%20software%20attacks.pdf
And someone went to silly lengths to fix a Furuno: https://tomverbeure.github.io/2024/08/18/Fixing-the-Symmetricom-S200-GPS-Week-Number-Rollover-Problem.html
Fun trivia, the Unix epoch rolls over in January of 2038, but the next GPS WNRO happens in Novermber of that same year. So some systems, if you hiccup the epoch past that, may immediately suffer Y2038 problems.
Yep! But it sadly cannot replace soldering for denser pinout layouts, unless a lot of pressure is applied. Someone tried though;
https://tomverbeure.github.io/2019/11/21/Z-tape.html
(A bit off topic but that Bloomberg story is still such a mystery to me. It went into quite a bit of details and claimed it had tons of sources, so even if it was a completely false story whoever fabricated it must have put insane amounts of efforts/identity fraud into the set up)
There are a couple hundred FOSS CPU designs actually:
https://tomverbeure.github.io/rtl/2018/12/06/The-VexRiscV-CPU-A-New-Way-To-Design.html
https://www.oracle.com/servers/technologies/opensparc-overview.html
https://opencores.org/projects?expanded=Processor
I agree that manufacturing is a real problem. FOSS processors can get adoption but until we open up the manufacturing pipeline they won't provide end users with the benefits we get from FOSS software.