Pepijn de Vos writes about hardware and software projects, including FPGA and PCB tools, Clojure, Lego analog computers, and Arduino hacks.
HN links it for hardware projects like compiling VHDL to 74xx logic PCBs and a Lego tide-predicting computer, and for his Clojure multiple index post.
In the video comments he posted a link [1] to his blog where he explains the design process using simulated annealing. Amazing how close he got to the targeted final ratios using only a sequential gear train.
[1] http://pepijndevos.nl/2022/01/30/predicting-the-tide-with-an-analog-computer-made-from-lego.html
>who insisted we build a virtual CPU using only fundamental components. No VHDL for us!
A little convoluted, but apparently a couple of people have coaxed Verilog and/or VHDL into understanding 74xx logic chips: http://pepijndevos.nl/2019/07/18/vhdl-to-pcb.html
This makes me wonder if there might be a project out there that can compile Verilog to a schematic or netlist for 74-series logic.
Edit: unsurprisingly, the answer is yes - http://pepijndevos.nl/2019/07/18/vhdl-to-pcb.html
SEEKING WORK, remote possible.
I love robots, hardware, Clojure and functional programing in general.
I also do mainstream stuff sometimes.
http://pepijndevos.nl
It's been done before (http://pepijndevos.nl/2019/07/18/vhdl-to-pcb.html see also Hackaday), but not exactly a standard use of yosys.
Another fun one is the multiple index problem:
http://pepijndevos.nl/2012/08/12/the-multiple-index-problem.html